1. Field of the Invention
The present invention relates to a digital processing system and, particularly, to a method and apparatus for bit operational process suitably used in an image processing system having a bit-map display.
2. Description of the Prior Art
The prior art system will first be described by taking an example of image processing shown in FIG. 1. In the figure, reference symbol M1 denotes a memory area storing image data in 1-to-1 correspondence to a CRT (Cathode Ray Tube) screen, M2 denotes a memory area storing image data to be added to the image data in M1, X.sub.A and X.sub.B denote partial areas in M1 and M2, respectively, for which image data processing takes place, W.sub.A0, W.sub.A1, W.sub.A2, W.sub.B0 and W.sub.B1 denote boundaries of data words having a word length of 16 bits, for example, R.sub.0 through R.sub.m represent raster lines for the partial areas X.sub.A and X.sub.B, na and nb represent displacements of the leading edges of the areas X.sub.A and X.sub.B from the word boundaries W.sub.A0 and W.sub.B0, respectively, A.sub.0 through A.sub.n and B.sub.0 through B.sub.n represent addresses of word data in the areas X.sub.A and X.sub.B, and MFY denotes a modification unit for implementing the alignment and processing for the areas X.sub.A and X.sub.B having different starting bit positions na and nb.
Since the currently available processing unit such as a microprocessor deals with data and makes access to the memory in units of a word or a byte, the memory areas M1 and M2 shown in FIG. 1 have a word or byte structure. However, in image processing, a partial screen area to be processed is specified from the outside of the system without regard to the word boundary as shown by areas X.sub.A and X.sub.B in FIG. 1. On this account, image processing for combining the partial areas X.sub.A and W.sub.B needs a modification unit MFY with the following three processing functions.
(1) Rearrangement of word data so that processing can take place on a word-wide basis between data for areas X.sub.A and X.sub.B with different starting bit positions na and nb. PA1 (2) Separation of data section from word-wide data e.g., na bits, in each of addresses A.sub.0, A.sub.3, . . . , A.sub.n-2 so that it is retained unchanged in the processing. PA1 (3) Data processing in any specific number of bits (bit width) so that monochrome display is implemented using one bit per pixel while color display uses a plurality of bits per pixel (generally four bits per pixel). PA1 (a) For SN&gt;DN: Rotate the SRC content left by a number of bits of SN-DN. PA1 (b) For SN&lt;DN: Rotate the SRC content right by a number of bits of DN-SN. PA1 (c) For SN=DN: No operation.
The operation of the modification unit having these functions will be described in connection with FIG. 2. Throughout the following description, it is assumed that the image data memory is addressed in units of a word.
FIG. 2 shows a 2-word register SRC(A) and SRC(B) for storing data read out of the processing area X.sub.B, a 2-word register DST(A) and DST(B) for storing data read out of the processing area X.sub.A, and a 2-word register DST(A) and DST(B) for storing the result of processing for the contents of the registers SRC(A, B) and DST(A, B). The modification unit MFY performs rotation of the register SRC(A, B), i.e., shift of SRC content with bit 0 of SRC(A) linked with bit F of SRC(B), depending on the values of SN (i.e., nb) and DN (i.e., na) representing the starting bit positions of the processing areas X.sub.A and X.sub.B, as follows.
In this way, bit addresses nb(SN) and na(DN) are used to align the operation starting bit position.
Consequently, the starting bit position of the SRC content is adjusted to that of the DST content. The bit width of processing, WN, is set in advance, and the remaining portion of data is left unchanged. Although in FIG. 2 the result register MRG(A, B) is provided independently of DST(A, B), they may be arranged in common. After the subsequent processing, the original bit position of the SRC content is restored automatically.
Next, the 4-bit image processing for the areas X.sub.A and X.sub.B by the modification unit MFY will be described in connection with FIGS. 3, 4, 5 and 6. The process shown in FIG. 3 includes step S1 of setting the starting address A.sub.0 for the processing area X.sub.A, step S2 of setting DN to the starting bit position (address) na, step S3 of setting the starting address B.sub.0 for the processing area X.sub.B, step S4 of setting SN to the starting bit position (address) nb, step S5 of the process implemented by the modification unit MFY mentioned above, steps S6-S9 for the area X.sub.B for obtaining the next bit address (S6), setting the next SN (S7), incrementing the address in word units (S8) and reading next word data (S9), and steps S10-S14 for the area X.sub.B for obtaining the next bit address (S10), setting the next DN (S11), writing the result of process in the register MRG(A) (S12), incrementing the address in word units (S13) and reading the next word data (S14). The process further includes decision steps SB1 and SB2, which implement the following operations.